Design and Implementation of Flexible Multiplier Using Razor Based Dynamic Voltage Scaling for Filter Design

In this paper, we present flexible multi-precision multiplier that combined variable precision, parallel processing (PP), razor based dynamic voltage scaling (DVS), and dedicated MP operand scheduling to provide optimum performance for variety of operating conditions. All of the building blocks of proposed flexible multiplier can either work as independent small precision multiplier or parallel to perform higher-precision multiplier. While still maintain full through-put, the dynamic voltage and frequency scaling management unit configures the multiplier to operate at the proper precision and frequency. Adapting to the run-time workload for targeted application, that flexible multiplier can used to design IIR filter for DSP application. Razor flip-flops together with a dithering voltage unit then configure the multiplier to achieve the lowest power consumption. The single-switch dithering voltage unit and razor flip-flops help to reduce the voltage margin and over head typically associated to DVS to lowest level. Finally, the proposed high speed flexible multiplier can further benefits from an operand scheduler that rearranges the input data, hence determine the optimum voltage and frequency operating conditions for minimum for power consumption. As well suited to design IIR filter design for DSP application. KeywordsComputer arithmetic, dynamic voltage scaling, low power design, multi-precision multiplier. I.Introduction Consumer demand for increasingly portable yet high performance multimedia and communication products impose stringent constraints on the power consumption of individual internal components [1].of these multiplier perform one of the most frequently encountered arithmetic operation in digital signal processor(DSPs)[2].Multiplier is typically designed for a fixed maximum word-length to suit the worst case scenario. However, the real effective word-lengths of an application vary dramatically. The use of a non-proper word length may cause performance degradation or inefficient usage of the hardware resources. In addition, the minimization of the multiplier power budget requires the estimation of the optimal operating point including clock frequencies, supply voltage, and threshold voltage [1].In most VLSI system designs, the supply voltage is also selected based on the worst case scenario. In order to achieve an optimal power/performance ratio, a variable precision data path solution is needed to cater for various types of applications. Dynamic Voltage Scaling (DVS) can be used to match the circuit’s real working load and further reduce the power consumption. Given their fairly complex structure and interconnections, multiplier can exhibits a large number of unbalanced paths, resulting in substantial glitch generation and propagation [8].this spurious switching activity can be mitigated by balancing internal paths through a combination of architectural and transistor-level Optimization techniques. In addition to equalizing internal path delays, dynamic power reduction can also be achieved by monitoring the INTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume V /Issue 2 /JULY 2015 IJPRES effective dynamic range of input operands so as to disable unused section of multiplier [6].therefore, an 8-bit multiplication computed on a 32-bit booth multiplier would result in unnecessary switching activity and power loss. Several works investigated this word-length optimization. [1], [2] proposed an ensemble of multiplier of different precision, with each pair of incoming operands is routed to the smallest multiplier that cancompute the result to take advantage of the lower energy consumption of the smaller circuit. This ensemble of point systems is reported to consume the least power but this came at cost increased chip area given the used ensemble structure. To address this issue,[3],[5] proposed to share and reuse some functional modules within the ensemble. In [3], an 8-bit multiplier is reused for the 16-bit multiplication adding scalability with out large area penalty. Reference [5] extended this method by implementing Pipelining to further improve the multiplier’s performance. A more flexible approach is proposed in [15]. Combining multi-precision (MP) with dynamic voltage scaling (DVS) can provide a dramatic reduction in power consumption by adjusting the supply voltage according to –Circuit’s runtime workload rather than fixing it to cater for the worst case scenario [2].when adjusting the voltage, the actual performance of multiplier running under scaled voltage has to be characterized to guarantee a fail-safe operation. Conventional DVS technique consist mainly of lookup table (LUT) the LUT approach tune the supply voltage according to predefined voltage frequency relationship stored in a LUT, which is formed worst case condition(process variation, power supply voltage droops, noise many more) therefore, large margin are necessarily added, which in turn necessary decrease effectiveness of DVS technique. Therefore, voltage could be scaled to the extent that the replica fails to meet the timing. However, safety margins are still needed to compensate for the intradie delay mismatch and address fast-changing transient effects [24].the aforementioned limitation of conventional DVS techniques motivated recent research efforts into error-tolerant DVS approaches [24]-[27], which can run-time operate the circuit even at a voltage level at which timing error occur, A recovery mechanism is then applied to detect and correct data. Because completely remove safety margins, errortolerant DVS techniques can further aggressively reduce power consumption. In this paper, we propose a low power reconfigurable multiplier architecture that combined MP with an error-tolerant DVS approach based on razor flip-flops [25], the main contributions of this paper can be summarized follows. Silicon area is optimized by apply reduction technique that replace a multiplier by adders/subtractors. a silicon implementation of this multi-precision multiplier integrating error tolerant razor based dynamic DVS approach. The run–time adaption to actual workload condition and allow minimum supply voltage and frequency, while meet throughput operation. A dedicated operand scheduler that rearrange operation on input operands so as to reduce the number of transitions of the supply voltage and, in turn, minimize the overall power consumption of the flexible multi-precision multiplier. A multiplier is an important part of digital signal processing systems, like frequency domain filtering (FIR and IIR), frequency-time transformations (FFT), Correlation, Digital Image processing etc. Multipliers have large area, long latency and consume considerable power. While many previous works focused on implementing high-speed multipliers, recently there have been many attempts to reduce power consumption [3]. This is due to the increased demand for portable multimedia applications, which require low power consumption as well as high speed. There is wide range of multipliers. Based on the way the data is processed, they are classified as serial, parallel and serial-parallel multipliers as shown in figure 1. INTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume V /Issue 2 /JULY 2015 IJPRES In parallel multipliers, there are two main classifications. They are array and tree multipliers. Tree multipliers add as many partial products in parallel as possible and therefore, are very high performance architecture. Unfortunately tree multipliers are very irregular, hard to layout and hence large. Array multipliers, on the other hand, are very regular, small in size but suffer in latency and propagation delay. Booth multiplier is used for signed binary numbers. They are also called radix-2 multiplier. Their main advantage is that it involves no correlation cycles for signed terms. But they become inefficient for alternate zeros and ones as it involves large numbers of adders and subtractors, his result in area and speed limitation. The problem is overcome with modified booth multiplier (MBM) or radix-4 multiplier which reduces the partial products by 50%. Thus it improves speed, reduce power consumption and also save multiplier layout area. MBM also has a regular structure. II. System Overview and Operation The proposed MP multiplier system (Fig. 2) comprises five different modules that are as follows: 1) The MP multiplier; 2)The input operands scheduler (IOS) whose function is to reorder the input data stream into a buffer, hence to reduce the required power supply voltage transitions; 3)The frequency scaling unit implemented using a voltage controlled oscillator (VCO). Its function is to generate the required operating frequency of the multiplier; 4)The voltage scaling unit (VSU) implemented using a voltage dithering technique to limit silicon area overhead. Its function is to dynamically generate the supply voltageso as to minimize power consumption; 5)The dynamic voltage/frequency management unit(VFMU) that receives the user requirements (e.g., throughput). The VFMU sends control signals to the VSU and FSU to generate the required power supply voltage and clock frequency for the MP multiplier. The MP multiplier is responsible for all computations. It is equipped with razor flip-flops that can report timing errors associated to insufficiently high voltage supply levels.The operation principle is as follows. Initially, the multiplier operates at a standard supply voltage of 3.3 V. If the razor flipflops of the multiplier do not report any errors, this means that the supply voltage can be reduced. This is achieved through the VFMU, which sends control signals to the VSU, hence to lower the supply voltage level. When the feedback provided by the razor flipflops indicates timing errors, the scaling of the power supply is stopped. Fig. 2. Overall multiplier system architecture. The proposed multiplier (Fig. 3) not only combines MP and DVS but also parallel processing (PP). Our multiplier comprises 8×8 bit reconfigurable multipliers. These building blocks can either work as nine independent multipliers or work in parallel to perform one, two or three 16×16 bit multiplications or a single-32×32 bit INTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume V /Issue 2 /JULY 2015 IJPRES operation. PP can be used to increase the throughput or reduce the supply voltage level for low power operation. Fig. 3.Possible configuration modes of existing MP multiplier Proposed Block for Multi-Precision Multiplier The following block diagram for proposed multiplier. Fig. 3.Possible configuration modes of proposed